1. Field of the Invention
The present invention relates to a magnetic memory device, and more specifically, it relates to a magnetic memory device including a storage element exhibiting ferromagnetic tunneling.
2. Description of the Background Art
An MRAM (magnetic random access memory), which is a nonvolatile memory recording data through magnetism is known in general. This MRAM is disclosed in detail in Nikkei Electronics, 1999. 11. 15 (No. 757), pp. 49-56 or the like.
FIGS. 9 and 10 are schematic diagrams for illustrating the structure of a storage element 110 of the MRAM disclosed in the aforementioned literature. Referring to FIG. 9, the storage element 110 of the conventional MRAM comprises a ferromagnetic layer 101, another ferromagnetic layer 103 and a nonmagnetic layer 102 arranged between the ferromagnetic layers 101 and 103.
The ferromagnetic layer 101 is harder to invert than the ferromagnetic layer 103. The term xe2x80x9cferromagnetismxe2x80x9d indicates magnetism in a case where magnetic atoms or free atoms of a metal orientate magnetic moments in parallel with each other by positive exchange interaction to form spontaneous magnetization, and a substance exhibiting this ferromagnetism is referred to as a ferromagnetic substance. The ferromagnetic layers 101 and 103 consist of such ferromagnetic substances. In general, a GMR (giant magnetoresistance) film employing a metal is employed as the nonmagnetic layer 102. A TMR (tunneling magnetoresistance) film employing an insulator is recently developed as the nonmagnetic layer 102. This TMR film advantageously has higher resistance than the GMR film. More specifically, the MR ratio (the rate of change of resistance) of the GMR film is in the 10% level, while that of the TMR film is at least 20%. The storage element 110 consisting of the TMR film is hereinafter referred to as a TMR element 110.
The storage principle of the conventional MRAM employing the TMR element 110 is now described with reference to FIGS. 9 and 10. As shown in FIG. 9, the state where the two ferromagnetic layers 101 and 103 are magnetized in the same direction (parallel) is associated with data xe2x80x9c0xe2x80x9d. As shown in FIG. 10, the state where the two ferromagnetic layers 101 and 103 are magnetized in the opposite directions (antiparallel) is associated with data xe2x80x9c1xe2x80x9d. The TMR element 110 exhibits small resistance (R0) when the directions of magnetization are parallel, while exhibiting large resistance (R1) when the directions of magnetization are antiparallel. xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d is determined through the resistance of the TMR element 110 varying with the parallel or antiparallel directions of magnetization.
FIG. 11 is a block diagram showing the overall structure of a conventional MRAM 150 having memory cells each formed by a TMR element and a transistor. The structure of the conventional MRAM 150 is now described with reference to FIG. 11.
A memory cell array 151 is formed by arranging a plurality of memory cells 120 in the form of a matrix (FIG. 11 shows only four memory cells 120 for simplifying the illustration). Each memory cell 120 is formed by a TMR element 110 and an NMOS transistor 111.
In the memory cells 120 arranged in a row direction, the gates of the NMOS transistors 111 are connected to common read word lines RWLa to RWLn. In the memory cells 120 arranged in the row direction, further, rewrite word lines WWLa to WWLn are arranged on first ferromagnetic layers of the TMR elements 110.
In the memory cells 120 arranged in a column direction, first ferromagnetic layers of the TMR elements 110 are connected to common bit lines BLa to BLn.
The read word lines RWLa to RWLn are connected to a row decoder 152, while the bit lines BLa to BLn are connected to a column decoder 153.
Externally specified row and column addresses are input in an address pin 154, and transferred from the address pin 154 to an address latch 155. In the addresses latched by the address latch 155, the row address is transferred to the row decoder 152 through an address buffer 156, and the column address is transferred to the column decoder 153 through the address buffer 156.
The row decoder 152 selects a read word line RWL corresponding to the row address latched by the address latch 155 from the read word lines RWLa to RWLn, while selecting a rewrite word line WWL corresponding to the row address latched by the address latch 155 from the rewrite word lines WWLa to WWLn. The row decoder 152 further controls the potentials of the read word lines RWLa to RWLn and the potentials of the rewrite word lines WWLa to WWLn on the basis of a signal from a voltage control circuit 157.
The column decoder 153 selects a bit line BL corresponding to the column address latched by the address latch 155 from the bit lines BLa to BLn, while controlling the potentials of the bit lines BLa to BLn on the basis of a signal from another voltage control circuit 158.
Externally specified data is input in a data pin 159 and transferred from the data pin 159 to the column decoder 153 through an input buffer 160. The column decoder 153 controls the potentials of the bit lines BLa to BLn in correspondence to the data.
Data read from an arbitrary memory cell 120 is transferred from any of the bit lines BLa to BLn to a sense amplifier group 161 through the column decoder 153. The sense amplifier group 161 is formed by current sense amplifiers. The data determined by the sense amplifier group 161 is output from an output buffer 162 through the data pin 159.
A control core circuit 163 controls operations of the aforementioned circuits 152 to 162.
Write (rewrite) and read operations of the conventional MRAM 150 having the aforementioned structure are now described.
Write Operation
In the write operation, orthogonal currents are fed to the selected rewrite word line WWL and the selected bit line BL. Thus, data can be rewritten only in the TMR element 110 located on the intersection between the bit line BL and the rewrite word line WWL. More specifically, the currents flowing through the rewrite word line WWL and the bit line BL generate magnetic fields, and the sum (combined magnetic field) of the two magnetic fields acts on the TMR element 110. This combined magnetic field inverts the directions of magnetization of the TMR element 110 from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d, for example.
The TMR elements 110 located on positions other than the aforementioned intersection include those fed with no currents and those only unidirectionally fed with currents. In each TMR element 110 fed with no current, no magnetic field is generated and hence the directions of magnetization remain unchanged. In each TMR element 110 only unidirectionally fed with a current, a magnetic field is generated in a magnitude insufficient for inverting the directions of magnetization. Therefore, the directions of magnetization remain unchanged in the TMR element 110 only unidirectionally fed with a current.
As hereinabove described, the directions of magnetization of the TMR element 110 located on the interposition between the selected bit line BL and the selected rewrite word line WWL can be changed as shown in FIG. 9 or 10 by feeding currents to the bit line BL and the rewrite word line WWL corresponding to the selected address. Thus, the data xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d can be written.
Read Operation
In order to read the data written in the aforementioned manner, a voltage is applied to the read word line RWL for rendering the NMOS transistor 111 conductive. In this state, determination is made as to whether or not the value of a current flowing through the bit line BL is larger than a reference current value, thereby determining xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
In this case, the directions of magnetization are parallel in the case of the data xe2x80x9c0xe2x80x9d shown in FIG. 9, and hence the resistance value (R0) is small. Therefore, the value of the current flowing through the bit line BL is larger than the reference current value. In the case of the data xe2x80x9c1xe2x80x9d shown in FIG. 10, on the other hand, the directions of magnetization are antiparallel and hence the resistance value (R1) is larger than that shown in FIG. 9. Therefore, the value of the current flowing through the bit line BL is smaller than the reference current value.
In the aforementioned conventional MRAM 150, the potential of the bit line BL must be set to a small level of not more than 0.4 V for detecting the current value in data reading. This is because resistance change of the TMR element 110 cannot be confirmed unless potential difference across the TMR element 110 is small. Therefore, the potential difference across the TMR element 110 must be small (not more than 0.4 V), leading to a small current value. The structure of the sense amplifier (amplifier) is disadvantageously complicated in order to detect such a small current value. Further, the reading speed is reduced when detecting the small current value.
An object of the present invention is to provide a magnetic memory device having a sense amplifier (amplifier) not complicated in structure.
Another object of the present invention is to provide a magnetic memory device capable of improving the reading speed as compared with a case of detecting a small current value for determining data.
A magnetic memory device according to an aspect of the present invention comprises a memory cell consisting of a storage element exhibiting ferromagnetic resistance and a transistor connected to the storage element, a word line connected to a control terminal of the transistor, a bit line connected to a first end of the storage element through the transistor, a reference bit line provided in common for a plurality of bit lines and an amplifier connected to the bit line and the reference bit line, for reading potential difference caused between the bit line and the reference bit line with the amplifier in data reading.
In the magnetic memory device according to this aspect, the memory cell is formed by a storage element exhibiting ferromagnetic resistance and a transistor while the amplifier detects the potential difference between the bit line connected to the storage element and the reference bit line as hereinabove described, whereby data can be readily read. Thus, no value of a small current flowing through the bit line may be detected dissimilarly to the prior art, whereby the structure of the amplifier is not complicated. The amplifier reads the potential difference caused between the bit line and the reference bit line, whereby data can be readily detected also when the storage element has high resistance dissimilarly to the prior art reading the value of the small current flowing through the bit line.
The magnetic memory device according to this aspect is so structured as to detect the potential difference between the bit line and the reference bit line with the amplifier as hereinabove described, whereby data stored in the magnetic memory device can be read through a simple amplifier similar to an amplifier (sense amplifier) employed for a conventional DRAM. Thus, no sense amplifier having a complicated structure may be employed dissimilarly to the prior art, whereby high-speed reading is enabled.
The magnetic memory device according to the aforementioned aspect preferably further comprises an auxiliary word line connected to a second end of the storage element for pulling down the potential on the second end of the storage element to a ground potential in response to rise timing of a signal toward the word line, for reading the potential difference caused between the bit line and the reference bit line at transient timing for lowering the potential of the auxiliary word line to the ground potential. According to this structure, the auxiliary word line can readily pull down the potential of the storage element toward the ground potential. The potential difference caused between the bit line and the reference bit line is read with the amplifier at the transient timing for lowering the potential of the auxiliary word line to the ground potential, whereby stored data can be readily detected.
In this case, the transient timing for lowering the potential of the auxiliary word line to the ground potential is preferably before the potential of the bit line and the potential of the reference bit line reach the ground potential. According to this structure, the potential difference between the bit line and the reference bit line can be prevented from disappearing. If the potential of the auxiliary word line reaches the ground potential, the potentials of the bit line and the reference bit line also reach the ground potential immediately thereafter, to exhibit no potential difference. When the amplifier detects the potential difference between the bit line and the reference bit line before the potentials of the bit line and the reference bit line reach the ground potential, therefore, the amplifier can detect the potential difference between the bit line and the reference bit line before the same disappears.
In the magnetic memory device according to the aforementioned aspect, the amplifier is preferably provided in common for a plurality of bit lines. According to this structure, the circuit structure can be simplified as compared with a case of providing the amplifier every bit line.
In the magnetic memory device according to the aforementioned aspect, the storage element exhibiting ferromagnetic resistance preferably includes a first magnetic layer and a second magnetic layer, arranged oppositely to the first magnetic layer through an insulating barrier layer, harder to invert than the first magnetic layer. According to this structure, data can be readily stored by setting the directions of magnetization of the first and second magnetic layers parallel or antiparallel in response to the data.
In the magnetic memory device according to the aforementioned aspect, the reference bit line preferably includes a reference memory cell provided every word line, and the reference memory cell preferably includes a first resistive element and a transistor connected to the first resistive element. According to this structure, the potential difference between the bit line including the memory cell and the reference bit line including the reference memory cell can be readily detected.
In this case, the first resistive element of the reference memory cell preferably has an intermediate resistance value between a resistance value attained when the directions of magnetization of the storage element are parallel and a resistance value attained when the directions of magnetization of the storage element are antiparallel. According to this structure, potential difference can be caused between the bit line and the reference bit line.
In this case, further, the first resistive element of the reference memory cell preferably includes two second resistive elements, exhibiting ferromagnetic resistance, having the resistance value attained when the directions of magnetization of the storage element are parallel and two third resistive elements, exhibiting ferromagnetic resistance, having the resistance value attained when the directions of magnetization of the storage element are antiparallel, and the second resistive elements and the third resistive elements are preferably serially connected respectively while pairs of the serially connected second resistive elements and third resistive elements are connected in parallel with each other. According to this structure, the resistance of the first resistive element of the reference memory cell connected to the reference bit line can be set to a value half the sum of the resistance value attained when the directions of magnetization of the storage element are parallel and that attained when the directions of magnetization of the storage element are antiparallel. Thus, potential difference can be readily caused between the bit line and the reference bit line. In this case, the storage element of the memory cell may include a TMR element, and the second resistive elements and the third resistive elements of the reference memory cell may include TMR elements.
In the aforementioned case, the first resistive element of the reference memory cell may include a second resistive element, exhibiting ferromagnetic resistance, having a resistance value substantially half the resistance value attained when the directions of magnetization of the storage element are parallel and a third resistive element, exhibiting ferromagnetic resistance, having a resistance value substantially half the resistance value attained when the directions of magnetization of the storage element are antiparallel, and the second resistive element and the third resistive element may be serially connected with each other. According to this structure, the resistance of the first resistive element of the reference memory cell connected to the reference bit line can be set to a value half the sum of the resistance value attained when the directions of magnetization of the storage element connected to the bit line are parallel and that attained when the directions of magnetization of the storage element are antiparallel. Thus, potential difference can be readily caused between the bit line and the reference bit line.
In this case, the storage element of the memory cell may include a TMR element, and the second resistive element and the third resistive element of the reference memory cell may include TMR elements. In this case, further, the second resistive element and the third resistive element of the reference memory cell may have areas twice that of the storage element of the memory cell.
In the aforementioned case, the first resistive element of the reference memory cell may have a resistance value substantially identical to either the resistance value attained when the directions of magnetization of the storage element are parallel or the resistance value attained when the directions of magnetization of the storage element are antiparallel. In this case, the load capacity of the bit line and the load capacity of the reference bit line may be different from each other. According to this structure, potential difference is caused between the bit line and the reference bit line also when the resistance value of the first resistive element is substantially identical to either the resistance value attained when the directions of magnetization of the storage element are parallel or that attained when the directions of magnetization of the storage element are antiparallel, whereby data can be readily determined. In this case, the gate widths of a pair of transistors forming the amplifier may be different from each other.
In this case, further, the first resistive element of the reference memory cell may have a resistance value substantially identical to the resistance value attained when the directions of magnetization of the storage element are parallel. Alternatively, the first resistive element of the reference memory cell may have a resistance value substantially identical to the resistance value attained when the directions of magnetization of the storage element are antiparallel.
In the magnetic memory device according to the aforementioned aspect, the storage element of the memory cell may include a TMR element. Further, the amplifier may include a cross-coupled latch type voltage sense amplifier.
The magnetic memory device according to the aforementioned aspect preferably further comprises a dummy bit line provided in common for a plurality of bit lines and a comparator connected to the dummy bit line through the transistor, and a dummy storage element having two magnetic layers so set that the directions of magnetization are parallel to each other is preferably connected to the dummy bit line. According to this structure, potential difference caused between the bit line and the reference bit line can be readily sensed through the dummy bit line and the comparator.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.